Figure 7
NAND logic circuit design and characteristics. (a) Circuit schematic of NAND device with zero-VGS-load p-type pseudo-CMOS design. (b) Photograph of fabricated NAND circuit. (c) Measured output voltage (VOUT) and small-signal gain as a function of input voltage B (VIN_B) for input voltage A VIN_A = 0 V and VIN_A = 10 V when VDD = − 10 V and VIN_A = 20 V when VDD = − 20 V. (d) Dynamic response of NAND logic circuit with input signals of frequencies, VIN_A = 0.5 kHz and VIN_A = 5 kHz.
