Figure 2 | Scientific Reports

Figure 2

From: Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

Figure 2

(a) Measured ID-VdGS characteristics from the fabricated ICDG NMOS for various |VcGS|. (b) Semi-empirically simulated ID-VdGS characteristics according to various |VcGS|. Superimposition of measured and simulated ID-VDS characteristics of N-channel for (c) |VcGS|= 0.4 V and (d) 1.5 V on the log-scaled y-axis and linear-scaled y-axis. (e) Linear Vth shift by VcGS. (f) Simulated ID-VdGS characteristics of both ICDG NMOS and PMOS for various |VcGS|.

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