Figure 4
From: NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors
VTCs demonstration with a certain sequence. (a) Dynamic VTCs of the NAND LIM sweeping VIN1 with pulse values of (a) VIN2 = 1.0 V. (b) Timing diagrams corresponding to the sequential dynamic VTCs. (c) Tables (c) summarize the performed logic operations. (d) Dynamic VTC of the NOR LIM in a sweep of VIN1 with pulse values of (d) VIN2 = 1.0 V. e, Timing diagrams corresponding to the sequential dynamic VTCs. (f) Tables (f) summarize the performed logic operations.
