Figure 2
Process flow for creation of multi-level structures using novel approach. (a) Clean bare wafer without features; (b) Intermediate ultra-thin masking material is deposited—in our case, SiO2 is CVD deposited; (c) Photoresist (PR) spinning is uniform, this process is not hindered because it is thicker than the underlying SiO2 layer, exposure of Design 1, and development; (d) Using PR as mask layer, the underlying SiO2 is etched to a precise amount, \({t}_{1}\); (e) Stripping PR; (f) Second round of lithography is performed—in this situation PR thickness is at least 1.5 times the maximum SiO2 feature thickness already on the wafer, thus spin coating process is successful, yielding a thin conformal coat all over the 3D featured SiO2. This time design 2 was etched in SiO2 to a different depth, \({t}_{2}\); (g) After two rounds of litho, a 2-level structure is made on the SiO2; (h) After two more rounds of litho, 2 more levels can be made. In theory, \(n\) rounds of lithography is able to make at least \(n\) levels in the structure; (i) The wafer with a 3D structured SiO2 layer is now etched in a deep Si Reactive Ion Etcher (RIE) to vertically scale the SiO2 3D pattern by the Si:SiO2 selectivity (which is around 200–300 for our case) and transfer to the silicon wafer underneath. Finally, we are left with an \(n\) level, high aspect ratio structure, deep structure in Si; (j) In contrast to the multi-level structure, this is a single-level structure shown for comparison.
