Figure 1

The integration process of the IGZO FET fabrication. Process sequence for (a–e) BG and (f–m) DG FET fabrication. SEM images of DG FET (n) after active patterning (g) and (o) after planarization (h). TEM images of DG FET (p) after gate patterning (j) and (q) after metallization (m).