Figure 4
Models for nVo(x) and n0(x) considering the device structure and process conditions, which are implemented by the TCAD device simulator for the (a) BG FET and the (b) DG FET structure.
Figure 4 | Scientific Reports
Models for nVo(x) and n0(x) considering the device structure and process conditions, which are implemented by the TCAD device simulator for the (a) BG FET and the (b) DG FET structure.
