Table 13 Results comparison for NAND gate.

From: Efficient design and analysis of secure CMOS logic through logic encryption

Encryption methodology

Switch count

Area, μm2

Power, nW

Delay, ps

PDP, aJ

Standard cell

4

2.44

216.5

36

7.79

Key based CMOS

6

3.64

252.6

52

13.13

XOR based CMOS

16

9.61

560.4

72

40.34

LUT based CMOS

32

19.18

754.4

90

67.89

Stack based CMOS

10

6.027

255.3

46

11.74

Proposed CMOS

6

3.64

225.7

40

9.02

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