Table 14 Results comparison for NOR gate.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Encryption methodology | Switch count | Area, μm2 | Power, nW | Delay, ps | PDP, aJ |
|---|---|---|---|---|---|
Standard cell | 4 | 2.44 | 219.8 | 40 | 8.79 |
Key based CMOS | 6 | 3.64 | 306.4 | 44 | 13.48 |
XOR based CMOS | 16 | 9.61 | 560.8 | 65 | 36.45 |
LUT based CMOS | 32 | 19.18 | 763.6 | 99.5 | 75.97 |
Stack based CMOS | 10 | 6.027 | 255.3 | 46 | 11.74 |
Proposed CMOS | 6 | 3.64 | 242 | 44 | 10.64 |
