Table 16 Results comparison for XNOR gate.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Encryption methodology | Switch count | Area, μm2 | Power, nW | Delay, ps | PDP, aJ |
|---|---|---|---|---|---|
Standard cell | 12 | 7.20 | 503.5 | 50 | 25.17 |
Key based XNOR PT without buffer | 16 | 9.61 | 692.3 | 87 | 60.23 |
Key based XNOR PT with buffer | 20 | 11.97 | 1200 | 89 | 106.8 |
XOR based | 24 | 14.36 | 1101 | 80 | 88.08 |
LUT based | 40 | 23.91 | 1393 | 119 | 165.76 |
Stack based | – | – | – | – | – |
Proposed XNOR/AND | 14 | 8.41 | 550 | 62 | 34.1 |
