Table 17 % of Changes for AND gate.

From: Efficient design and analysis of secure CMOS logic through logic encryption

Encryption methodology

% Area

I/R

% Power

I/R

% Delay

I/R

% PDP

I/R

Standard cell

25

R

1.92

R

4.44

R

6.287

R

Key based

0

–

7.13

I

2.173

I

9.149

I

XOR based

55.14

I

49.92

I

31.81

I

65.860

I

LUT based

76.20

I

65.83

I

55

I

84.624

I

Stack based

32.86

I

10.94

I

11.76

I

21.418

I

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