Table 19 % of Changes for NAND gate.

From: Efficient design and analysis of secure CMOS logic through logic encryption

Encryption methodology

% Area

I/R

% Power

I/R

% Delay

I/R

% PDP

I/R

Standard cell

32.8

R

4.076

R

10

R

13.66

R

Key based

0

–

10.64

I

23.07

I

31.26

I

XOR based

62.03

I

59.72

I

44.44

I

77.62

I

LUT based

80.98

I

70.08

I

55.55

I

86.70

I

Stack based

39.47

I

11.59

I

13.04

I

23.12

I

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