Table 20 % of Changes for NOR gate.

From: Efficient design and analysis of secure CMOS logic through logic encryption

Encryption methodology

% Area

I/R

% Power

I/R

% Delay

I/R

% PDP

I/R

Standard cell

32.8

R

9.17

R

9.09

R

17.43

R

Key based

0

–

21.01

I

0

–

21.01

I

XOR based

62.03

I

56.84

I

32.30

I

70.78

I

LUT based

80.98

I

68.30

I

55.77

I

85.98

I

Stack based

39.47

I

5.20

I

4.34

I

9.33

I

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