Table 23 Analysis of design overheads for XOR based logic encryption along with % of improvements when compared with proposed logic encryption.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Gate | Area (μm2) | Power (nW) | Delay (ps) | PDP (aJ) |
|---|---|---|---|---|
AND | 10.79 (55.14%) | 559.2 (49.92%) | 66 (31.81%) | 36.90 (65.86%) |
OR | 10.79 (55.14%) | 560.9 (46.33%) | 80 (43.75%) | 44.87 (69.81%) |
NAND | 9.61 (62.03%) | 560.4 (59.72%) | 72 (44.44%) | 40.34 (77.62%) |
NOR | 9.61 (62.03%) | 560.8 (56.84%) | 65 (32.30%) | 36.45 (70.78%) |
XOR | 14.36 (41.45%) | 1056 (52.96%) | 80 (17.25%) | 84.48 (61.07%) |
XNOR | 14.36 (41.45%) | 1101 (50.04%) | 80 (22.5%) | 88.08 (61.28%) |
Average | 52.87% | 52.63% | 32% | 67.73% |
