Table 24 Analysis of design overheads for LUT based logic encryption along with % of improvements when compared with proposed logic encryption.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Gate | Area (μm2) | Power (nW) | Delay (ps) | PDP (aJ) |
|---|---|---|---|---|
AND | 20.34 (76.2%) | 819.5 (65.83%) | 100 (55%) | 81.95 (84.62%) |
OR | 20.34 (76.2%) | 829.3 (63.7%) | 100 (55%) | 82.93 (83.66%) |
NAND | 19.18 (80.98%) | 754.4 (70.08%) | 90 (55.55%) | 67.89 (86.70%) |
NOR | 19.18 (80.98%) | 763.6 (68.3%) | 99.5 (55.77%) | 75.97 (85.98%) |
XOR | 23.91 (64.82%) | 1326 (62.54%) | 101 (34.45%) | 133.92 (85.31%) |
XNOR | 23.91 (64.82%) | 1393 (60.51%) | 119 (47.89%) | 165.76 (79.42%) |
Average | 74% | 65.16% | 50.61% | 84.28% |
