Table 25 Analysis of design overheads for Stack based logic encryption along with % of improvements when compared with proposed logic encryption.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Gate | Area (μm2) | Power (nW) | Delay (ps) | PDP (aJ) |
|---|---|---|---|---|
NAND-NOR | 6.027(39.47%) | 255.3 (11.69%) | 46 (13.04%) | 11.74 (23.12%) |
AND-OR | 7.2 (32.86%) | 314.4 (10.94%) | 51 (11.76%) | 16.03 (21.41%) |
Average | 36.16% | 11.26% | 12.4% | 22.26% |
