Table 26 Analysis of design overheads for Key based logic encryption along with % of improvements when compared with proposed logic encryption.
From: Efficient design and analysis of secure CMOS logic through logic encryption
Gate | Area (μm2) | Power (nW) | Delay (ps) | PDP (aJ) |
|---|---|---|---|---|
AND | 4.84 (0%) | 301.5 (7.13%) | 46 (2.173%) | 13.86 (9.149%) |
OR | 4.84 (0%) | 304.1 (1.01%) | 46 (2.17%) | 13.98 (3.17%) |
NAND | 3.64 (0%) | 252.6 (10.64%) | 52 (23.07%) | 13.13 (31.26%) |
NOR | 3.64 (0%) | 306.4 (21.01%) | 44 (0%) | 13.48 (21.01%) |
XOR ST | 13.17 (36.17%) | 1081 (54.05%) | 80 (17.25%) | 86.48 (61.97%) |
XOR PT | 9.61 (12.48%) | 697.5 (28.78%) | 75 (11.73%) | 52.31 (37.14%) |
XNOR PT | 9.61 (12.48%) | 692.3 (20.55%) | 87 (28.73%) | 60.23 (43.38%) |
Average | 8.73% | 20.45% | 12.16% | 29.58% |
