Figure 9
From: FPGA-based CCD signal acquisition and transmission system design
(a) Timing diagram of \({V}_{SH}\), \({V}_{ICG}\), \({V}_{\varphi M}\). (b) Timing diagram of \({V}_{SH}\), \({V}_{ICG}\), \({V}_{\varphi M}\). (c) Timing diagram of \({V}_{SH}\), \({V}_{ICG}\), \({V}_{\varphi M}\).
