Table 1 Control timing chart.
From: FPGA-based CCD signal acquisition and transmission system design
Characteristic | Symbol | Min (ns) | Max (ns) |
|---|---|---|---|
\({V}_{ICG}\) pulse delay | t1 | 1000 | – |
Pulse timing of \({V}_{SH}\) and \({V}_{ICG}\) | t2 | 100 | 1000 |
\({V}_{SH}\) pulse width | t3 | 1000 | – |
Pulse timing of \({V}_{ICG}\) and \({V}_{\varphi M}\) | T4 | 0 | – |
