Table 2 Robustness verification results.
Test Scenario | Injection Method | Fault Tolerance Threshold (ms) | Recovery Success Rate(%) | Maximum Recovery Time (ms) |
---|---|---|---|---|
Clock drift attack | T_SM_local\(\:+=\varvec{\delta\:}\varvec{t}\) | \(\:\varvec{\delta\:}\varvec{t}\le\:3\) | 98.7 | 15 |
Data processor crash | Randomly set DPM_done = false | N/A | 95.2 | 30 |
Communication delay | Transmission delay + 5ms | \(\:\le\:5\) | 99.1 | 10 |
Multi-module concurrent faults | Combination of the above faults | Comprehensive | 90.3 | 45 |