Table 3 Summary of various existing hardened latch designs.

Delta DICE⁹

Eftaxiopoulos, N.

et al., (2015)

Data is maintained on

three interconnected

DICEs, with shared

nodes to improve

error recovery

DNU self-recovery

is provided, and the

D-Q delay is

reduced utilizing an

inverter

TNU cannot be

tolerated, and the

various feedback

loops result in high

power consumption

TNURL²⁴

A. Yan

et al.(2020)

Employs seven SIMs

to improve TNU

recoverability

through redundant

data storage

By using

interconnected SIMs,

it assures reliability

of data and exhibits

strong resilience

Significant area

overhead and power

consumption; it is

vulnerable to quasi-

node disruptions

because of its lack of

QNU tolerance

IHTRL²⁵

Huang Z,

et al., (2021)

Enhance stability by

integrating a 4 × 4 

C-element array, four

clock-gated CEs,

and four

transmission gates

Exhibits high error

tolerance and

lower delay

Its complex matrix

design results in a

significant area

overhead, and the

significance for high-

speed applications is

limited by its

propagation delay

(D-Q)

HTNURE²⁶

Xu H.,

et al., (2021)

Comprises twelve 2-

input CEs and six

pass gates, design

with a three-loop

interlocked feedback

system

Maintains precise

data inputs by using

feedback loops that

are interconnected

Multiple feedback

loops result in

significant power

consumption; a long

recovery stage

reduces

effectiveness in

real-time applications

LTNUT²⁷

. Lu Y,

et al., (2022)

Enhances SEU

protection through

the combination of

an ISEHL latch

with multi-level C-

elements

Extremely efficient

for space

applications, which

provides total

defence against SEU

for all nodes within

including output

Multiple error-filtering

stages result in

significant power

consumption, and the

complex circuit

design causes

fabrication to be

more difficult

QNUTL²⁸

A. Yan,

et al., (2022)

QNU tolerance can

be obtained by using

a triple-level Soft-

Error-Interceptive

Module (SIM) and

three DICE cells

Can maintain QNU

events while

enhancing the

reliability in radiation

conditions

Higher power

consumption and

circuit complexity;

incomplete QNU self-

recovery, which

could result in

latching problems in

extreme cases

HLTNURL²⁹

Y. Dai.,

et al., (2022)

Increases TNU

resilience by using

a timing clock-gating

method and

feedback system

Provides strong

TNU protection

while maintaining data

integrity under fault

conditions caused

on by radiation

Complex feedback

as well as recovery

connects lead to high

power consumption;

integration in small

nano electronic

systems is limited by

a large silicon area

LCTNUCR³⁰

S. Cai,

et al., (2023)

It utilizes multiple

clocked four-input

C-elements to

improve upset

recovery

Achieves TNU self-

recovery and

provides strong fault

tolerance in

radiation-sensitive

environments

A high transistor

counts results in

excessive area

overhead making

integration into large-

scale circuits is

challenging due to

complex design

ADTRL³¹

A. Yan,

et al., (2023)

Uses three modified

DICE cells and six

transmission gates

are employed to

improve fault

tolerance

Reduces power

consumption

compared to other

TNU-resilient latches

while offering robust

node-upset

resilience

The modified DICE

structure increases

design complexity,

eventually resulting

in greater area and

minimum delay

TSRL³²

Y. Bai,

et al., (2024)

A quadrilateral

recovery structure

which includes four

clock-gated dual-

input CEs and twelve

dual-input CEs

Recoverable from

any possible TNUs

with a robust error

correction system

The use of several

dual-input CEs

results in a large

area overhead and

prolonged recovery

periods for TNU

faults