Table 7 Power and delay values corresponding to variations in CNT positions.
From: Low power and high-speed quadrate node upset tolerant latch design using CNTFET
CNT Pos | -2 | -1 | 0 | 1 | 2 |
|---|---|---|---|---|---|
Power (µW) | 4.394 | 4.394 | 4.395 | 4.395 | 4.395 |
Delay (D-Q)ps | 1.227 | 1.227 | 1.227 | 1.228 | 1.288 |
