Fig. 1: PG-NDT device featuring a controllable potential barrier and/or well.
a Schematic and optical microscopy images of the PG-NDT device with a partially defined gate electrode (top) and energy band diagram showing a controllable potential barrier and/or well formed under positive and negative gate bias conditions (bottom). b 3D AFM mapping image of the PG-NDT device (top) and thickness profiles of the WSe2 and h-BN layers at the yellow dotted line (bottom). c ID−VG characteristic curves of conventional vdW transistor with a fully defined gate (top) and the PG-NDT device with a partially defined gate (bottom). d Gm−VG characteristic curves showing the positive differential transconductance and negative-differential transconductance phenomena. e Peak and valley voltages extracted from NDT characteristic curves, which were consistently observed in four different PG-NDT device samples (top) and in the PG-NDT device samples fabricated with various vdW channels (bottom).
