Fig. 1: Tunneling detector scheme and electrical characterization.
a The stack scheme of the tunneling detector. b Optical photograph of the sample with false-color images of the top, bottom graphene, and barrier hBN superimposed on it. Contacts to the top and bottom graphene used in measurements are designated by the letters “T” and “B” accordingly. AFM scan of barrier hBN edge is shown in the inset. There is a cutout in the stack made to avoid possible shorting of the top and bottom graphene. Scale bar is 10 μm. c Ib−Vb device characteristics at different gate voltages, showing ladder-type behavior. d Map of differential conductance as a function of bias and gate voltages at 7 K. The curves of maximum conductance are marked with i1t, i2t, i1b, i2b, and arrows of minimum conductance—cnpt, cnpb and blue dotted lines. The black dotted lines correspond to the theory. e Illustration of the tunneling process when the 1st impurity is aligned with the bottom graphene Fermi level, which corresponds to the i1b-curve on (d). f Same illustration, but the impurity is aligned with the bottom graphene CNP (cnpb-curve on (d)).
