Extended Data Fig. 1: Calibration procedure for gate leakage measurements.
From: A cryogenic CMOS chip for generating control signals for multiple qubits
a, Quantum dot device used to extract gate leakage. Gates used are highlighted in red, and the current path used for the measurement is shown by the green arrow. b, Sample calibration trace, taken by sweeping the voltage on the LW gate, while the charge lock switch GHOLD is closed. The extraction process for gate voltage is indicated by arrows. c, The measured current through the QPC when the charge locking switch is opened. d, The extracted gate voltage held on the gate for a period of 30 minutes.
