Fig. 1: Industrially fabricated QD devices.
a, High-angle annular dark-field scanning transmission electron microscopy image of a typical device. The active region consists of two parallel silicon fins: one hosts the qubits and the other hosts the sensing dot. The fan-out of the gates is clearly visible, as well as the many additional metallic structures (called dummification) needed to maintain a roughly constant density of metal on the surface, which ensures homogeneous polishing on the wafer scale. b, TEM image along a Si fin, showing seven metallic finger gates to define the QD array and two accumulation gates (ACL and ACR) to induce reservoirs connecting to the phosphorus n-type implants that serve as ohmic contacts (outside the image). The gates are isolated from the fin by a composite SiO2 and high-k dielectric layer. A SiO2 ILD is located between the gates for isolation. c, False-coloured TEM image perpendicular to the Si fins, showing the silicon fins and SiO2 STI fill in between the fins. d, Schematic of the active region of the device. e, Schematic of the process steps used to fabricate the devices: Si fin formation (i); STI planarization (ii); poly-silicon dummy-gate patterning and n+ implants for source/drain formation (iii); ILD deposition for gate-spacer formation, planarization, dummy-gate removal and first gate-layer formation (iv); ILD etch to open a window for the second gate layer and second gate-layer formation (v); ILD deposition, trench formation and metal fill for contacting the gates and implants and ESR line formation (vi).
