Extended Data Fig. 2: Yield maps for wafers 11-14.

Each 300-mm wafer consists of 82 die and each die contains quantum dot arrays with various design skews and array sizes (up to 55 gates), as well as transistor and calibration test structures. To analyse cross-wafer sample yield, automated probing at room temperature is used to measure one seven-gate device per die (nominally identical to the devices discussed in the main text). For each device, the turn on voltage (when biasing all gates with the same voltage) and the threshold voltage for each of the seven gates (sweeping down one gate voltage at a time while keeping the other gate voltages above the turn-on voltage) on both fins are analysed. Moreover, the workings of the ion-implanted ohmic contacts are tested. If the device shows turn on, pinch-off for each gate and the ohmic contacts work, the device is labeled ‘functioning’ (green). In any other case, the device is labeled non-functioning and discarded (red). In total, we studied 20 wafers. All wafers were fabricated with different process parameters. Out of the 20 wafers, the production process of wafers a. 11, b. 12, c. 13 and d. 14 was almost identical, apart from the modification of some etching and polishing steps per wafer for process optimization. For wafer 11, the polishing was pushed outside the optimal process window, resulting in a lower yield. For all four wafers, the non-yielding devices are found around the edge of the wafer.