Extended Data Fig. 3: Characterizations of the electrical stability of 3D integrated interfaces of various stretchable logic circuits.
a, Design of the permeable stretchable logic circuits including inverse gate, NOR gate, and clock-controlled switch. b, Outputs of the logics validated with the rigid printed circuit boards. c and d, Digital images of the inverse gate and NOR gate, respectively. e and f, Logic outputs of the inverse gate, and NOR gate respectively. g, Schematic illustration of the permeable 3D integrated stretchable switch array. h, Threshold driving voltage of the switch array at a strain of 100%. i, Statistic analysis of the transconductance of the 64-channel switch array. j, Digital images of the permeable 3D integrated stretchable switch array at 100% strain. The switches were used for controlling loads and in complementary metal-oxide semiconductor (CMOS) digital circuits as they operated between their cut-off and saturation regions. The multi-channel switch array showed a uniform threshold driving voltage (Vg) of ~1.75 V at a strain of 50%, and an average transconductance of ~100 mS.
