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Integration of high-κ native oxides of gallium for two-dimensional transistors

Abstract

The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from quality issues that can compromise transistor performance. Here, we show that an ultrathin and uniform native oxide of gallium (Ga2O3) that naturally forms on the surface of liquid metals in an ambient environment can be prepared on the surface of molybdenum disulfide (MoS2) by squeeze-printing and surface-tension-driven methods. The Ga2O3 layer possesses a high dielectric constant of around 30 and equivalent oxide thickness of around 0.4 nm. Due to the good dielectric properties and van der Waals integration, MoS2 transistors with Ga2O3 gate dielectrics exhibit a subthreshold swing down to 60 mV dec−1, an on/off ratio of 108 and a gate leakage down to around 4 × 10−7 A cm−2.

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Fig. 1: Integration of Ga2O3 as a dielectric layer.
Fig. 2: Device configuration of a top-gated MoS2 FET with a Ga2O3 dielectric layer.
Fig. 3: Dielectric properties of Ga2O3.
Fig. 4: MoS2 FET performance with Ga2O3 dielectric layer.
Fig. 5: Logic gates with a Ga2O3 dielectric layer.

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Data availability

The data that support the findings of this study are available from the corresponding authors upon reasonable request.

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Acknowledgements

Z.L. acknowledges support from the National Research Foundation, Singapore, under its Competitive Research Programme (Grant No. NRF-CRP22-2019-0007) and its NRF-ISF joint research program (Grant No. NRF2020-NRF-ISF004-3520). This research is also supported by A*STAR under an AME IRG grant (Project No. A2083c0052) and A*STAR MTC Programmatic Grant (Grant No. M23M2b0056). The microwave microscopy work (S.F. and K.L.) is supported by the Welch Foundation (Grant No. F-1814). The nanoindentation work (Q.F. and J.L) is supported by the Welch Foundation (Grant No. C-1716).

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Authors and Affiliations

Contributions

Z.L. and K.Y. conceived and designed the project. K.Y. performed the OM, AFM, ultraviolet–visible spectroscopy, X-ray photoelectron spectroscopy, device fabrication, electrical measurements and data analysis. Y.H., Y.W., X.C. and Y. Dong contributed to the preparation of focused-ion-beam samples and cross-sectional STEM characterizations. W.Q., Z.H. and Z.Z. performed the DFT calculations. Y.W. performed the STEM, EDS and electron energy loss spectroscopy characterizations. S.F. and K.L. performed the tuning-fork-based microwave impedance microscopy measurements. Q.F. and J.L. performed the indentation measurements. X.Z., T.L. and X.W. provided the wafer-scale MoS2. K.-W.A. helped with the low-temperature measurements. Y. Deng prepared the CVD MoS2 single crystals and performed the Raman measurements. C.Z. commented on the manuscript and helped analyse the data. K.K.-Z. helped revise the manuscript. K.Y. and Z.L. summarized the manuscript. All authors contributed to discussions.

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Correspondence to Kongyang Yi or Zheng Liu.

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Nature Electronics thanks Mohammad Bagher Ghasemian, Yuxuan Cosmi Lin and He Tian for their contribution to the peer review of this work.

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Supplementary Table 1 and Figs. 1–40.

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Surface-tension-driven preparation.

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Yi, K., Qin, W., Huang, Y. et al. Integration of high-κ native oxides of gallium for two-dimensional transistors. Nat Electron 7, 1126–1136 (2024). https://doi.org/10.1038/s41928-024-01286-x

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