Fig. 5: Reliability studies of SLCFET at the latching condition along with its practical application.

a, Methodology adopted for stress testing of latching condition. The device was stressed for 90 min in steps of 2 min and I_D–V_GS at V_DS = 0.1 V to monitor the device condition. b, The evolution of I_D and I_G as a function of stressing time at V_DS = 12 V and V_GS = −11.5 V. Inset: the mean value of I_D and I_G over each 2-min cycle. c, The monitored I_D and g_m as function of V_GS at V_DS = 0.1 V after each stress cycle in the latching condition. d, The I_D, g_m and \({g}_{{\rm{m}}}^{{\prime\prime} }\) of the SLCFETs are plotted when biased at V_DS of 8 V (unlatched condition) and 12 V (latched condition). Current compliance for I_D was set to 200 mA. The normalization in d was performed by dividing the measured I_D by the active source width of the device, which was approximately 50% of entire width. This was to have a one-to-one comparison with similar fin-based devices in the literature, for example, ref. ⁴³.