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Gate stack engineering of two-dimensional transistors

Nature Electronics volume 8, pages 770–783 (2025)Cite this article

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Abstract

Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.

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Fig. 1: CMOS transistor roadmap and potential of 2D transistors.
Fig. 2: Interface-engineered MOS gate stacks in 2D transistors and their characteristics.
Fig. 3: Benchmarking key performance metrics of 2D MOSFETs against IRDS targets.
Fig. 4: FE-embedded gate stacks in 2D transistors.
Fig. 5: Future directions and perspectives in gate stack integration for more-Moore and beyond-CMOS 2D electronics.

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Acknowledgements

This Review was supported by the National Research Foundation of Korea (NRF) (grant nos. 2023R1A2C3005923, RS-2023-00258309 and 2022M3H4A1A01010280). C.-H.L. acknowledges the support from BK21 FOUR programme of the Education and Research Program for Future ICT Pioneers, Seoul National University (SNU) in 2024, Creative-Pioneering Researchers Program, New Faculty Startup Fund from SNU, and SNU Electrical Power Research Institute (SEPRI). J.L. acknowledges support from the Institute of Information & Communications Technology Planning & Evaluation (IITP) under the Artificial Intelligence Semiconductor Support Programme to Nurture the Best Talents (IITP-2023-RS-2023-00256081) grant funded by the Korea government (MSIT).

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Authors and Affiliations

  1. KU-KIST Graduate School of Converging Science and Technology, Korea University, Seoul, Republic of Korea

    Yeon Ho Kim & Gunuk Wang

  2. Department of Chemistry, Kookmin University, Seoul, Republic of Korea

    Donghun Lee

  3. Semiconductor R&D Center, Samsung Electronics Co. Ltd., Hwaseong, Republic of Korea

    Woong Huh, Jaehyun Park & Daewon Ha

  4. Department of Electrical and Computer Engineering, Seoul National University, Seoul, Republic of Korea

    Jaeho Lee, Donghyun Lee & Chul-Ho Lee

  5. Inter-university Semiconductor Research Center, Seoul National University, Seoul, Republic of Korea

    Chul-Ho Lee

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Contributions

C.-H.L. conceptualized and structured the overall paper. C.-H.L. and Y.H.K. wrote the main body of the paper. D.H., J.P. and W.H. provided insights on future technological directions from an industrial perspective. Donghun Lee, G.W. J.L. and Donghyun Lee contributed to analysing previous research, organizing the figures and partially to the writing.

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Kim, Y.H., Lee, D., Huh, W. et al. Gate stack engineering of two-dimensional transistors. Nat Electron 8, 770–783 (2025). https://doi.org/10.1038/s41928-025-01448-5

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