Fig. 1: Schematic representation of the proposed chip.
From: Scaling advantage of chaotic amplitude control for high-performance combinatorial optimization
Schematic representation of a conventional central processing unit (CPU) and separate memory with the von Neumann bottleneck problem and b the proposed neuromorphic chip for combinatorial optimization. Universal Asynchronous Receiver/Transmitter (UART), phase-locked loops (PLL), and global clock buffer with clock enable (BUFGCE) are used for input/output of data, clock management, and clock gating, respectively. Neurons and synapses are shown in the bottom to illustrate the analogy between the organization of the chip and biological neural networks. Schema of dynamics in analog state-space x of algorithms based on c annealing on a potential function shown at different times ti and d a trajectory of proposed chaotic amplitude control scheme shown by the curved gray line with an arrow. Red circles show the discrete space σ.
