Fig. 3: Time to solution of the field programmable gate array (FPGA) implementation for Sherrington-Kirkpatrick instances.
From: Scaling advantage of chaotic amplitude control for high-performance combinatorial optimization
a Lower, higher, and upper whisker of boxes show the 50th, 80th, and 90th percentiles of the time to solution \({\tau }_{q}^{* }\) distribution in seconds vs. the square root of problem size \(\sqrt{N}\) for the FPGA implementation of chaotic amplitude control (CAC) with a maximum of 5W power consumption and the following algorithms running on a CPU (20W): CAC, simulated annealing (SA), and parallel tempering (PT). b The same as a for the energy-to-solution E*. Power consumption of the FPGA is considered constant with respect to N because of the pipelined implementation.
