Fig. 2: Circuit description and measured anomalous impedance scaling.

a Our circuit is an N × N square lattice array with the horizontal and vertical links being capacitors C and inductors L, respectively. The corner-to-corner impedance Z is measured by running a current between the lower left and upper right (N-th) nodes. The scaling behavior of Z is revealed to contrast strongly with the logarithmic scaling of a similar but uniform circuit array consisting of only one type of element, i.e., resistors (shown in the inset) or capacitors. b We implement our LC circuit arrays on circuit boards and control the lattice size N through switches. Shown here is the 6 × 6 case—our board shown here admits up to the N = 7 case. c In principle, with purely capacitive or inductive LC components, the corner-to-corner impedance of our circuit becomes drastically higher by a few orders at particular lattice sizes N, and depends sensitively on \({\omega }_{r}=\omega \sqrt{LC}\) according to Eq. (3). d These anomalous corner-to-corner impedance peaks are attenuated in our experimental measurements but are still robustly prominent, as shown in these plots at three illustrative AC frequencies ω. The measured (exp, red) data agrees well with the simulated values (sim, cyan) with estimated parasitic resistances (estimated to be R_pL = 3.3 Ω, R_pC = 4.5 Ω, R_pW = 0.1 Ω, see “Methods: Analysis of uncertainties”), and are captured by a complex effective ω_r with Im(ω_r) of the order of 10⁻². This contrasts with uniformly capacitive circuits (all-cap, dark magenta), which exhibit logarithmic scaling with no non-monotonic peaks.