Fig. 9: QFT adder with QCL. | Communications Physics

Fig. 9: QFT adder with QCL.

From: Constrained optimization via quantum Zeno dynamics

Fig. 9

Quantum circuits for (a) semiclassical quantum Fourier transform adder with quantum conditional logic (QCL) used in the hardware experiments involving equality constraints and (b) the four-qubit rotation gate used in a. Note that R(α) denotes a phase gate. For the equality-constraint experiment executed on the H1-2 quantum device, we set a ≔ (a1, a2, a3, a4) = (2, − 1, − 1, 0). The uncomputation step consists of resetting the auxiliary qubit to the \(\left\vert +\right\rangle\) state.

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