Fig. 5: Further acceleration of computation using a supercell.

The computational time (simulated on a CPU for FPGA) per MC sweep for (a), the XY model on square lattice, b the XY model with NNN interactions on square lattice, (c), the XY model on square-octagonal lattice and d, the Ising model on square-octagonal lattice, with the system lattice sizes \(N=\) 16, 64, 144, 256, 1024, and 4096. The black triangles, red squares, and orange pentagons represent the computational time for FPGA in sequential style, in pipelined parallel style with 4 sites in one unit cell, and pipelined parallel style with a supercell, respectively. In (d), the cases \(N=\) 16 and 64 were verified on our FPGA chip, labeled as solid pentagons. The gray dashed lines represent the fitted results with \({aN}+b\). The ratios \(b/a\) extracted from the results of the pipelined parallel style with 4 sites in one unit cell, are shown at the center of each panel. The insets in the bottom-right corner illustrate the lattice configurations.