Table 1 Gate times and simulated fidelities for silicon qubits at T = 1.05 K.

From: Design and integration of single-qubit rotations and two-qubit gates in silicon above one Kelvin

 

Gate time (ns)

Fideal(%)

Fnoise(%)

CROT

660

99.4

89.0

CPHASE

152

99.9

97.8

Diabatic CPHASE

67

99.9

99.4

SWAP

19

84.3

84.2

Composite SWAP

89

99.9

99.4

  1. Gate times and simulated fidelities for all the two-qubit gates discussed in the main text, where Fideal represents the fidelity in the absence of noise and Fnoise takes into account the experimental noise at 1.05 Kelvin. We find high-fidelity two-qubit gates can be obtained in silicon above one Kelvin, by using diabatic CPHASE or composite SWAP sequences. The CROT fidelity is calculated as a conditional π-flip for better comparison. Good agreement is obtained with previous experiments19, confirming that the simulated noise is an accurate estimate of the real noise. Further improvement in the fidelities of the CROT and the CPHASE may be obtained by incorporating pulse shaping34,35,36,37,38.
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