Extended Data Fig. 5: Digital logic gates based on an all-metal three-terminal electrical switch.
From: Anomalous in-plane electrical anisotropy in elemental metal nanosheets
(a) Schematic of an anisotropic-metal-based three-terminal device for driving a logic gate. The device has two perpendicular input terminals (IN1(\({{V}_{d}}^{\perp }\)), IN2(\({{V}_{d}}^{\,{||}}\))) and one output terminal (|Is|). (b) |Is|–\({{V}_{d}}^{\,{||}}\) curves for the IN1 = 0 (\({{V}_{d}}^{\perp }\) = 0 mV, gray curve) and IN1 = 1 (\({{V}_{d}}^{\perp }\) = ± 5 mV, blue curves) states. The blue dashed line indicates |Is|th = 4×10−8 A. (c) Numerical prediction of |Is|–\({{V}_{d}}^{\,{||}}\) curves with (\({{V}_{d}}^{\perp }\) = 5 mV) and without (\({{V}_{d}}^{\perp }\) = 0 V) \({{V}_{d}}^{\perp }\) depending on the electrical anisotropy (Rxx/Ryy). As the electrical anisotropy increases, the magnitude of the curve shift (Vshift) increases. The numerical approach involving variations in electrical anisotropy (Rxx/Ryy) is conducted while maintaining a constant Ryy = 1.89 × 105 Ω. (d-h) Truth tables (upper table) and schematics of output current levels (|Is|) for the four input states ((IN1, IN2) = (0,0), (0,1), (1,0), and (1,1)) on the |Is|–\({{V}_{d}}^{{||}}\) curves (bottom graph) of (d) OR, (e) NAND, (f) NOR, (g) XNOR, and (h) XOR gates. (i-m) Logic input (IN1, IN2) (two upper graphs) and measured output current levels (|Is|) (bottom graph) for the logic behaviors of the (i) OR, (j) NAND, (k) NOR, (l) XNOR, and (m) XOR gates. The four continuously changing (IN1, IN2) states ((0,0), (0,1), (1,0), and (1,1)) have 20 measurements each with intervals of 60 ms, for a total of 4800 ms. The blue dashed line indicates |Is|th = 4×10−8 A.
