Fig. 2: Nanowire processing and physical characterization.
From: Vertical GeSn nanowire MOSFETs for CMOS beyond silicon
a Cross-sectional transmission electron microscopy (TEM) micrograph of the Ge/GeSn/Ge heterostructure used for fabrication of vertical n-FETs (n-VFETs), overlapped with secondary ion mass spectrometry (SIMS) depth profiles of Sn, Ge and P. b 3-D scanning electron microscopy (SEM) image of a top-down n-type nanowire (NW). In the upper inset, the spin-on-glass (SOG) is etched to evidence the gate stack -Ge source region. The lower inset shows the top of the NW after the second SOG planarization prior to NiGe contact formation. c Overlapped SEM images of GeSn/Ge NWs used for p-VFETs. d Cross-sectional TEM image of a vertical Ge0.95Sn0.05/Ge GAA NW n-VFET. Insets of d Energy-dispersive X-ray spectroscopy (EDX) elemental mapping of Ni, Ti, and Sn metals (upper left), High-resolution-TEM (HR-TEM) image showing the sharp interface between GeSn and the GeSnOx/Al2O3/5 nm HfO2 gate stack (bottom left) and the GeSn/Al2O3 interface (bottom right). e EDX elemental mapping of a p-VFET with HR-TEM images for the top NiGeSn/GeSn source contact (left top) and for the GeOx/Al2O3/5 nm HfO2 gate oxides on Ge channel.
