Fig. 5: On-chip solar cell with surface electrode optimization.
From: On-chip solar power source for self-powered smart microsensors in bulk CMOS process
a The horizontal and vertical cross-sectional views of a conventional triple-well on-chip solar cells. b The micrograph of the conventional triple-well on-chip solar cell. c The layout of the proposed deeply segmented triple-well on-chip solar cell with the center electrode (CE) and N+ as interconnection. d The micrograph of the proposed deeply segmented triple-well on-chip solar cell. e The cross-sectional views of the proposed deeply-segmented triple-well solar cell sub-cells. f The measurement results of the load curve and power curve for the two 0.01 mm2 triple-well on-chip solar cells. Device I is conventional one and Device II is the proposed one.
