Fig. 1: General architecture of the logarithmic Bayesian machine. | Communications Engineering

Fig. 1: General architecture of the logarithmic Bayesian machine.

From: The logarithmic memristor-based Bayesian machine

Fig. 1

a General schematic of the computations of a Bayesian machine. b, c Simplified schematic of the implemented logarithmic and stochastic Bayesian machines. All log-probabilities in the logarithmic machine are coded as eight-bit integers, following Eq. (4).

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