Fig. 2: Details of the hardware realization of the logarithmic Bayesian machine. | Communications Engineering

Fig. 2: Details of the hardware realization of the logarithmic Bayesian machine.

From: The logarithmic memristor-based Bayesian machine

Fig. 2

a Optical microscopy image of the die of the fabricated machine. b Detail of the likelihood block, which consists of digital circuitry and memory block with its periphery circuit. c Photograph of the 2T2R memristor array. d Scanning electron microscopy image of a memristor in the back end of the line of our hybrid memristor/CMOS process.

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