Fig. 3: Circuits of the logarithmic Bayesian machine and memristor characterization.
a Schematic of the likelihood block is presented in Fig. 2b. b Schematic of the differential pre-charge sense amplifier (PCSA) used to read the binary memristor states. c Error rate of the 2T2R approach as a function of the error rate of the 1T1R approach. The different points are obtained by varying memristor programming conditions on a 1024-memristor array (results reproduced from ref. 35, see main text). d Schematic of the level shifter. e Cumulative distribution function of the resistance of memristors for the two programmed states: low resistance state (LRS) and high resistance state (HRS), measured on a 1024-memristor array (see the “Methods” section).
