Fig. 4: Demonstration and implementation of 4-bit S-Box based on automatic synthesis algorithm. | Communications Engineering

Fig. 4: Demonstration and implementation of 4-bit S-Box based on automatic synthesis algorithm.

From: Mixed-mode in-memory computing: towards high-performance logic processing in a memristive crossbar array

Fig. 4

a Block diagram and comparison of cell numbers between proposed solution and CMOS implementation from ref. 49. GF denotes Galois Field. b Control sequence provided by M3S using BiFeO3 based memristive crossbar. Each VI3 operation is noted as v in the diagram. The red and blue shadowed cycles are VI and MI cycles, respectively. c Demonstration of sequential operations with arbitrary inputs. d Experimental results with input Ahex (x1−4 = 1010) and output Fhex (y1−4 = 1111). The results of the memristance of each cell Mi, the voltage on WL to shared bottom electrode VWL, the voltage on BL to top electrode VBLi, and the absolute values of the current ∣Ii∣ across each cell during operation are demonstrated.

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