Fig. 8: Schematic of the traditional SOT-MRAM design featuring margins in the SOT track.

a An extreme SOT design with no margins is proposed to prevent power consumption within these margins. b Illustration of energy consumption (E_SW) of devices with varying margins in width or length. The extreme devices exhibit the lowest E_SW at 79 fJ/bit. c Endurance measurements conducted for 50% lifetime analysis using bipolar pulses under SOT stress for (left) various track widths with MTJ CD = 63 nm and (right) track lengths with MTJ CD = 81 nm. Figure are reprinted with the permission from ref. ¹⁰⁸, copyright 2023 by IEEE.