Fig. 2: Hardware implementation of random EdgeConv layers and intrinsic stochasticity of memristor.
From: Random memristor-based dynamic graph CNN for efficient point cloud learning at the edge
a Schematic of random EdgeConv splitting to reduce parameter count. We split one EdgeConv layer into two sub-layers. b Hardware implementation of in-memory matrix multiplication on memristor macro. Inputs are converted to voltages and fed into bit-lines, carrying vector-matrix multiplication via Ohm’s and Kirchhoff’s laws. Output currents from source lines are accumulated from memristor array and reference resistor output. c Optical photos of the memristor array and cross-sectional Transmission Electron Micrograph (TEM) of a single 1-transistor-1-memristor cell (scale bar: 200 nm and 50 nm). d Physical origin of intrinsic stochasticity in memristor. e Conductance map of memristor sub-array. f Histogram of the conductance. g Retention of memristors.
