Figure 1
From: Tunable transport gap in narrow bilayer graphene nanoribbons
Schematic illustration of the fabrication procedures to obtain dual-gated bilayer graphene nanoribbon FET.
(a), Si/Al2O3 core/shell nanowires are transferred onto a bilayer graphene sheet. (b), Source and drain electrodes are formed on aligned bilayer graphene and Si/Al2O3 core/shell nanowires. (c), Uncovered bilayer graphene is etched by oxygen plasma and bilayer graphene nanoribbons are produced underneath Si nanowires. (d), A thin film of 60 nm HfO2 is deposited by e-beam evaporation to prevent electrical breakdown of plasma damaged SiO2. (e), Top gate electrode is deposited as a final process. (f), Schematic of the cross-sectional view of the device.
