Figure 4
From: Isolated nanographene crystals for nano-floating gate in charge trapping memory
CV measurements for the MANGOS structure.
(a) Schematic cross-section of the MANGOS device structure (up) and the corresponding band diagram of the retention states before and after program operation (down). The blocking layer is 15-nm Al2O3 deposited by ALD. After the deposition of the blocking layer, RTA annealing at 1000°C for 1 min in N2 ambient was carried out. 200-nm Al gate was used as the gate electrode. Control sample of metal/Al2O3/SiO2/Si (MAOS) structure was also prepared by the same process. (b) Raman spectra of nanographene before and after RTA. (c) High frequency CV characteristics of MANGOS under different gate voltage sweepings. (d) Data retention for MANGOS.
