Figure 4 | Scientific Reports

Figure 4

From: Individual Zn2SnO4-sheathed ZnO heterostructure nanowires for efficient resistive switching memory controlled by interface states

Figure 4

Schematic representation of the band alignment for RS of n-type Zn2SnO4/n-type ZnO core/shell heterojunction.

(a) Before contact. (b) At a zero or relatively low bias voltage, the presence of interface states induces the depletion region with high barrier near the heterointerface and forms a back-to-back contacted diode for the core ZnO. (c) At a relatively high bias voltage, the interface states are filled near the electrode subjected to a negative voltage, resulting into a disappearance of interface potential barrier, the device changes from HRS into LRS. However, the interface states are created near the electrode subjected to a positive voltage and correspondingly, electrons are injected from the interface states into the electrode and the interface potential barrier increases and the energy band moves upward. The insets on the top of (b) and (c) are the schematic diagrams of corresponding electric circuit.

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