Figure 2
From: Electron transport of WS2 transistors in a hexagonal boron nitride dielectric environment
(a) shows plots of I-V for a 4 L WS2 device on a 20 nm thick h-BN crystal before and after sweeoubg the voltage bias to large values (see supplementary information). The inset shows the circuit used for decreasing the contact resistance. (b–d) are plots of the gate dependence of the conductivity for a monolayer WS2 flake on SiO2 substrate (b), for a four layer WS2 flake on SiO2 substrate (c) and for a 4 layer WS2 flake on h-BN substrate (d). All the sweeps in (b–d) were made at the same rate of 100 V/hr. The inset in (d) shows a micrograph picture of a WS2 transistor with scale bar of 5 um.
