Figure 1

The basic design of the magnetic skyrmion logic gate system.

(a), Sketch of the simulated model: the red and green layers represent the nanowire and the substrate, respectively; the spin-polarized current is injected into the nanowire with the current-in-plane (CIP) geometry, through which electrons flow from the source to the drain, i.e., toward +x; the current density inside the wide part of the nanotrack is proportional to the current density inside the narrow part of the nanotrack with respect to the ratio of narrow width to wide width; a skyrmion is initially created at the input side and can be pushed into the output side by the current with the conversion between skyrmion and domain-wall pair in the junction geometry. (b), The top-view of the design of the 1-nm-thick skyrmion-conversion geometry: the width of the input and output sides is 150 nm, the width of the narrow channel is 12 nm and the length of the sample is 450 nm; the interface connection angle is fixed at 45 degrees (similarly hereinafter); red and blue denote two regions with different parameters, where a gradient transition of parameter is used on the narrow channel. (c), The top-view of the design of the 1-nm-thick geometry for the skyrmion duplication: the width of all the input and output sides is 100 nm and the length of the sample is 600 nm. (d), The top-view of the design of the 1-nm-thick geometry for the skyrmion merging and the logical OR gate: the geometry is the horizontally-flipped version of the one in c. e, The top-view of the design of the 1-nm-thick geometry for the logical AND gate: the geometry is similar to the one in d, except the horizontal branch of the Y-junction channel, of which the width is increased from 20 nm to 40 nm. The current density inside the output side is equal to the sum of that inside the two input sides. All the designed samples can connect to nanowires with matching width of the branch for application in integrated circuit devices.